1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device such as a nonvolatile semiconductor memory device having a boosting circuit for generating an internal voltage by boosting a supply voltage.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as NAND type flash memory, an internal voltage generating circuit is provided because an internal voltage higher than the supply voltage is needed in data writing and erasing operation. This internal voltage generating circuit includes a boosting circuit for boosting the supply voltage to a required internal voltage, and a voltage detecting circuit. The voltage detecting circuit compares the monitor voltage obtained by dividing the output voltage of the boosting circuit with a specified reference voltage in a comparative amplifier, and feeds back the detection output of the result to the boosting circuit. The detection output of the voltage detecting circuit is a signal for controlling the boosting circuit to start/stop the boosting operation of the supply voltage, and is used for maintaining the output voltage of the boosting circuit at a specified internal voltage level. In a general conventional NAND type flash memory, during writing sequence operation, the output voltage of the boosting circuit is always held higher than the writing voltage level (see, for example, patent document 1: Japanese Patent Application Laid-Open No. 11-353889).
However, the writing sequence operation includes a write operation and a write verify operation, and the writing voltage is actually used in the write operation only among the writing sequence operation. Therefore, maintaining such high voltage in the boosting circuit means continuous flowing of current in the voltage detecting circuit, which may lead to increase of current consumption. Especially, when multiple values are stored for setting a plurality of threshold levels in one memory cell, the write verify operation is repeated plural times for one write operation, and thus the write verify time is very long, and the wasteful consumption of power spent during this period cannot be ignored.
To solve the problem, a prior art has been disclosed in patent document 2 (Japanese Patent Application Laid-Open No. 2007-80478).
This prior art has a plurality of switching elements provided in a current passage in the boosting circuit and voltage detecting circuit for activating or inactivating the boosting circuit and voltage detecting circuit. In the write verify operation, these switching elements are turned off, whereby the boosting circuit and the voltage detecting circuit are inactivated, so that the current consumption is curtailed.